Intel 64 Architecture Memory Ordering

Intel 64 memory ordering guarantees that for each of the following memory-access instructions, the constituent memory operation appears to execute as a single memory access regardless of memory type:


  1. Instructions that read or write a single byte.

  2. Instructions that read or write a word (2 bytes) whose address is aligned on a 2 byte boundary.

  3. Instructions that read or write a doubleword (4 bytes) whose address is aligned on a 4 byte boundary.

  4. Instructions that read or write a quadword (8 bytes) whose address is aligned on an 8  byte boundary.

All locked instructions (the implicitly locked xchg instruction and other read-modify-write  instructions with a lock prefix) are an indivisible and uninterruptible sequence of load(s) followed by store(s) regardless of memory type and alignment.
Other instructions may be implemented with multiple memory accesses. From a memory ordering point of view, there are no guarantees regarding the relative order in which the constituent memory accesses are made. There is also no guarantee that the constituent operations of a store are executed in the same order as the constituent operations of a load

Intel 64 memory ordering obeys the following principles:


  1. Loads are not reordered with other loads.

  2. Stores are not reordered with other stores.

  3. Stores are not reordered with older loads.

  4. Loads may be reordered with older stores to different locations but not with older
    stores to the same location.

  5. In a multiprocessor system, memory ordering obeys causality (memory ordering
    respects transitive visibility).

  6. In a multiprocessor system, stores to the same location have a total order.

  7. In a multiprocessor system, locked instructions have a total order.

  8. Loads and stores are not reordered with locked instructions.

http://www.multicoreinfo.com/research/papers/2008/damp08-intel64.pdf

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Tomasz Kulig